1. Field of the Invention
The present invention relates to computer systems having memory and memory controllers to access the memory and supply data to a datapath.
2. Description of Related Art
In typical computer systems, a memory controller is coupled to the processor for controlling memory access to RAM. Particularly, the processor supplies an address, and the memory controller is responsible for accessing the RAM and controlling storage of the data in a data path. The performance of many microprocessor systems can be improved by increasing the rate at which data can be read from its random access memory (RAM).
Conventional low-cost RAM devices include dynamic RAM (DRAM), such as page mode DRAMs. In order to improve memory access time using the low-cost page mode DRAMs, bank-interleaved designs have been used.
In bank-interleaved designs, multiple banks of page mode DRAMs are coupled to the memory controller and the datapath. A two-bank bank-interleaved device achieves a burst rate twice that of a single bank alone. For example, if the burst rate is four clock cycles for the first bank and the second bank individually, then a two cycle clock rate can be achieved by alternating memory access between the two banks. Disadvantages of the bank-interleaved configuration include a higher pin count and additional logic to handle the interleaved operations.
High-cost synchronous DRAM based designs are also available. Synchronous DRAM devices can be very fast. However, these devices are expensive and it would be an advantage to provide a system that uses lower cost DRAMs while still providing a high burst rate.
A new type of DRAM device, termed a "Extended Data Out" (EDO) DRAM has recently been introduced. Theoretically, such devices can achieve better burst performance at lower cost than page mode DRAMs. However, achieving the maximum rate can be difficult due in part to the timing requirements of these EDO DRAMs in a system environment. EDO DRAMs extend the length of time over which the data becomes available. However, the data does not become available until much later in the cycle, and the availability continues until the next cycle. The delayed availability creates problems in strobing the accessed data and capturing valid data in the datapath device.
It would be an advantage to provide a memory system including EDO DRAMs that increases their performance and the burst rate systems using these EDO DRAMs.